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A3955 Full-Bridge PWM Microstepping Motor Driver
Features and Benefits
1.5 A continuous output current 50 V output voltage rating Internal PWM current control 3-bit nonlinear DAC Fast, mixed fast/slow, and slow current-decay modes Internal transient-suppression diodes Internal thermal shutdown circuitry Crossover-current and UVLO protection
Description
The A3955 is designed to drive one winding of a bipolar stepper motor in a microstepping mode. The outputs are rated for continuous output currents to 1.5 A and operating voltages to 50 V. Internal pulse width modulated (PWM) current control combined with an internal three-bit nonlinear digitalto-analog converter allows the motor current to be controlled in full-, half-, quarter-, or eighth-step (microstepping) modes. Nonlinear increments minimize the number of control lines necessary for microstepping. Microstepping provides increased step resolution, and reduces torque variations and resonance problems at low speed. Internal circuitry determines whether the PWM current-control circuitry operates in a slow (recirculating) current-decay mode, fast (regenerative) current-decay mode, or in a mixed current-decay mode in which the off-time is divided into a period of fast current decay and with the remainder of the fixed off-time spent in slow current decay. The combination of user-selectable current-sensing resistor and reference voltage, digitally selected output current ratio; and slow, fast, or mixed current-decay modes provides users with a broad, variable range of motor control.
Continued on the next page...
Packages:
Package B, 16-pin DIP with exposed tabs Not to scale
Package LB, 16-pin SOIC with internally fused pins
Functional Block Diagram
LOGIC SUPPLY LOAD SUPPLY OUTA OUTB
PHASE 7
6 VCC
10
15
16
VBB GROUND 4 5 12 13
UVLO & TSD
MIXED-DECAY COMPARATOR
PWM LATCH
BLANKING GATE
CURRENT-SENSE COMPARATOR
SENSE 11
PFD
1
+ -
BLANKING
R Q S +- RC 3 V TH 2
REF
+ - /3 D/A
DISABLE
VCC
RS 8
D2
9
D1
14
D0
RT
CT
Dwg. FP-042
29319.41E
A3955
Description (continued)
Full-Bridge PWM Microstepping Motor Driver
Internal circuit protection includes thermal shutdown with hysteresis, transient-suppression diodes, and crossover-current protection. Special power-up sequencing is not required. The A3955 is supplied in a choice of two power packages; a 16-pin dual-in-line plastic package with copper heat-sink tabs (suffix `B'), Selection Guide
Part Number
A3955SB-T A3955SLB-T A3955SLBTR-T
and a 16-lead plastic SOIC with internally fused pins (suffix `LB'). For both package styles, the thermally enhanced pins are at ground potential and need no electrical isolation. Both packages are lead (Pb) free, with leadframe plating 100% matte tin.
Packing
16-pin DIP with exposed thermal tabs 16-pin SOICW with internally fused pins 16-pin SOICW with internally fused pins
Package
25 per tube 47 per tube 1000 per reel
Absolute Maximum Ratings
Characteristic Load Supply Voltage Logic Supply Voltage Logic/Reference Input Voltage Range Sense Voltage Output Current, Continuous Package Power Dissipation Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VBB VCC VIN VS IOUT PD TA TJ(max) Tstg Range S Fault conditions that produce excessive junction temperature will activate the device's thermal shutdown circuitry. These conditions can be tolerated but should be avoided. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C. Notes Rating 50 7.0 -0.3 to VCC + 0.3 1.0 1.5 See graph -20 to 85 150 -55 to 150 Units V V V V mA W C C C
Thermal Characteristics
Characteristic Package Thermal Resistance, Junction to Ambient Package Thermal Resistance, Junction to Tab Symbol RJA Test Conditions*
2 B Package, single-layer PCB, 1 in. 2-oz. exposed copper
Value 43 67 6
Units C/W C/W C/W
LB Package, 2-layer PCB, 0.3 side
2 in.
2-oz. exposed copper each
RJT
*Additional thermal information available on Allegro website.
ALLOWABLE PACKAGE POWER DISSIPATION (W)
4
R JT = 6.0C/W
3
SUFFIX 'B', R JA = 43C/W
2
1
SUFFIX 'LB', R JA = 67C/W
0 25 50 75 100 TEMPERATURE IN C 125 150
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A3955
Full-Bridge PWM Microstepping Motor Driver
ELECTRICAL CHARACTERISTICS at TA = 25C, VBB = 5 V to 50 V, VCC = 4.5 V to 5.5 V (unless otherwise noted.)
Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units
Power Outputs
Load Supply Voltage Range Output Leakage Current VBB ICEX VCE(SAT) Operating, IOUT = 1.5 A, L = 3 mH VOUT = VBB VOUT = 0 V Output Saturation Voltage (Forward or Reverse Mode) VS = 1.0 V: Source Driver, IOUT = -0.85 A Source Driver, IOUT = -1.5 A Sink Driver, IOUT = 0.85 A Sink Driver, IOUT = 1.5 A Sense Current Offset Clamp Diode Forward Voltage (Sink or Source) Motor Supply Current (No Load) ISO VF IBB(ON) IBB(OFF) D0 = D1 = D2 = 0.8 V IS - IOUT, IOUT = 850 mA, VS = 0 V, VCC = 5 V IF = 0.85 A IF = 1.5 A -- -- -- -- 20 -- -- -- -- 1.0 1.3 0.5 1.3 33 1.2 1.4 2.0 1.0 1.2 1.5 0.6 1.5 40 1.4 1.7 4.0 50 V V V V mA V V mA A VCC -- -- -- <1.0 <-1.0 50 50 -50 V A A
Continued next page...
Table 1 -- PHASE Truth Table
PHASE H L OUTA H L OUTB L H D2 H H H H VPFD 3.5 V 1.1 V to 3.1 V 0.8 V Description Slow Current-Decay Mode Mixed Current-Decay Mode Fast Current-Decay Mode L L L L
Table 3 -- DAC Truth Table
DAC DATA D1 D0 H H L L H H L L H L H L H L H L Current Ratio, % 100 92.4 83.1 70.7 55.5 38.2 19.5 VREF/VS 3.00 3.25 3.61 4.24 5.41 7.85 15.38
Table 2 -- PFD Truth Table
All Outputs Disabled
where VS = ITRIP*RS. See Applications section.
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A3955
Full-Bridge PWM Microstepping Motor Driver
ELECTRICAL CHARACTERISTICS (continued) at TA = 25C, VBB = 5 V to 50 V, VCC = 4.5 V to 5.5 V (unless otherwise noted. )
Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units
Control Circuitry
Logic Supply Voltage Range Reference Voltage Range UVLO Enable Threshold UVLO Hysteresis Logic Supply Current Logic Input Voltage Logic Input Current Mixed-Decay Comparator Trip Points ICC(ON) ICC(OFF) VIN(1) VIN(0) IIN(1) IIN(0) VPFD VIN = 2.0 V VIN = 0.8 V Slow Current-Decay Mode Mixed Current-Decay Mode Fast Current-Decay Mode Mixed-Decay Comparator Input Offset Voltage Mixed-Decay Comparator Hysteresis Reference Input Current Reference Divider Ratio Digital-to-Analog Converter Accuracy* Current-Sense Comparator Input Offset Voltage* Step Reference Current Ratio VIO(PFD) VIO(PFD) IREF VREF/VS -- VIO(S) SRCR VREF = 0 V to 2.5 V at trip, D0 = D1 = D2 = 2 V 1.0 V < VREF 2.5 V 0.5 V < VREF 1.0 V VREF = 0 V D0 = D1 = D2 = 0.8 V D0 = 2 V, D1 = D2 = 0.8 V D0 = 0.8 V, D1 = 2 V, D2 = 0.8 V D0 = D1 = 2 V, D2 = 0.8 V D0 = D1 = 0.8 V, D2 = 2 V D0 = 2 V, D1 = 0.8 V, D2 = 2 V D0 = 0.8 V, D1 = D2 = 2 V D0 = D1 = D2 = 2 V D0 = D1 = D2 = 0.8 V VCC VREF Operating Operating VCC = 0 5 V 4.5 0.5 3.35 0.30 -- -- 2.0 -- -- -- 3.5 1.1 -- -- 5.0 -- -- -- -- -- -- -- -- -- -- -- -- -- 5.0 -- 3.70 0.45 42 12 -- -- <1.0 <-2.0 -- -- -- 0 25 -- 3.0 -- -- -- 0 19.5 38.2 55.5 70.7 83.1 92.4 100 5.5 2.5 4.05 0.60 50 16 -- 0.8 20 -200 -- 3.1 0.8 20 55 5.0 -- 3.0 4.0 5.0 -- -- -- -- -- -- -- -- V V V V mA mA V V A A V V V mV mV A -- % % mV % % % % % % % %
Continued next page...
* The total error for the VREF/VS function is the sum of the D/A error and the current-sense comparator input offset voltage.
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A3955
Full-Bridge PWM Microstepping Motor Driver
ELECTRICAL CHARACTERISTICS (continued) at TA = 25C, VBB = 5 V to 50 V, VCC = 4.5 V to 5.5 V (unless otherwise noted. )
Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units
Control Circuitry (cont'd)
Thermal Shutdown Temp. Thermal Shutdown Hysteresis TJ TJ -- -- 165 15 -- -- C C
AC Timing
PWM RC Fixed Off-time PWM Turn-Off Time tOFF RC tPWM(OFF) CT = 470 pF, RT= 43 k Current-Sense Comparator Trip to Source OFF, IOUT = 100 mA Current-Sense Comparator Trip to Source OFF, IOUT = 1.5 A PWM Turn-On Time tPWM(ON) IRC Charge ON to Source ON, IOUT = 100 mA IRC Charge ON to Source ON, IOUT = 1.5 A PWM Minimum On Time Crossover Dead Time tON(min) tCODT VCC = 5.0 V, RT 43 k, CT = 470 pF IOUT = 100 mA 1 k Load to 25 V 18.2 -- -- -- -- 1.0 0.3 20.2 1.0 1.4 0.4 0.55 1.6 1.5 22.3 1.5 2.5 0.7 0.85 2.2 3.0 s s s s s s s
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A3955
Full-Bridge PWM Microstepping Motor Driver
Note the A3955SB (DIP) and the A3955SLB (SOIC) are electrically identical and share a common terminal number assignment.
Terminal Functions
Terminal 1 2 3 4-5 6 7 8 9 10 11 12-13 14 15 16 Name PFD REF RC GROUND Description (Percent Fast Decay) The analog input used to set the current-decay mode. (VREF) The voltage at this input (along with the value of RS and the states of DAC inputs D0, D1, and D2) set the peak output current. The parallel combination of external resistor RT and capacitor CT set the off time for the PWM current regulator. CT also sets the blanking time. Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage measurements. The PHASE input determines the direction of current in the load. (DATA2) One-of-three (MSB) control bits for the internal digital-to-analog converter. (DATA1) One-of-three control bits for the internal digital-to-analog converter. One-of-two output load connections. Connection to the sink-transistor emitters. Sense resistor RS is connected between this point and ground. Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage measurements. (DATA0) One-of-three (LSB) control bits for the internal digital-to-analog converter. One-of-two output load connections. (VBB) Supply voltage for the load.
LOGIC SUPPLY (VCC) Supply voltage for the logic circuitry. Typically = 5 V. PHASE D2 D1 OUTA SENSE GROUND D0 OUTB LOAD SUPPLY
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A3955
Full-Bridge PWM Microstepping Motor Driver
which turns off the source drivers (slow-decay mode) or the sink and source drivers (fast- or mixed-decay mode). With the DATA input lines tied to VCC, the maximum value of current limiting is set by the selection of RS and VREF with a transconductance function approximated by: ITRIP VREF / 3RS. The actual peak load current (IPEAK) will be slightly higher than ITRIP due to internal logic and switching delays. The driver(s) remain off for a time period determined by a user-selected external resistor-capacitor combination (RTCT). At the end of the fixed off-time, the driver(s) are re-enabled, allowing the load current to increase to ITRIP again, maintaining an average load current. The DAC data input lines are used to provide up to eight levels of output current. The internal 3-bit digital-to-analog converter reduces the reference input to the current-sense comparator in precise steps (the step reference current ratio or SRCR) to provide half-step, quarter-step, or "microstepping" load-current levels. ITRIP SRCR x VREF/3RS
Functional Description
Two A3955 full-bridge PWM microstepping motor drivers are needed to drive the windings of a bipolar stepper motor. Internal pulse width modulated (PWM) control circuitry regulates each motor winding current. The peak motor current is set by the value of an external current-sense resistor (RS), a reference voltage (VREF), and the digital-to-analog converter (DAC) data inputs (D0, D1, and D2). To improve motor performance, especially when using sinusoidal current profiles necessary for microstepping, the A3955 has three distinct current-decay modes: slow decay, fast decay, and mixed decay.
PHASE Input. The PHASE input controls the direction of current flow in the load (table 1). An internally generated dead time of approximately 1 s prevents crossover currents that could occur when switching the PHASE input.
to digitally control the output current. The output of the DAC is used to set the trip point of the current-sense comparator. Table 3 shows DAC output voltages for each input condition. When D0, D1, and D2 are all logic low, all of the power output transistors are turned off.
DAC Data Inputs (D0, D1, D2). A non-linear DAC is used
Slow Current-Decay Mode. When VPFD 3.5 V, the
device is in slow current-decay mode (the source drivers are disabled when the load current reaches ITRIP). During the fixed off-time, the load inductance causes the current to recirculate through the motor winding, sink driver, ground clamp diode, and sense resistor (see figure 1). Slow-decay mode produces low ripple current for a given fixed off-time (see figure 2). Low ripple current is desirable because the average current in the motor winding is more nearly equal to the desired
Internal PWM Current Control. Each motor driver
contains an internal fixed off-time PWM current-control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink transistors are enabled and current flows through the motor winding and RS (figure 1). When the voltage across the sense resistor equals the DAC output voltage the current-sense comparator resets the PWM latch,
V BB
I PEAK
SLOW (VPFD 3.5 V) MIXED (1.1 V V PFD 3.1 V)
DRIVE CURRENT RECIRCULATION (SLOW-DECAY MODE) RECIRCULATION (FAST-DECAY MODE)
PFD
FAST (V PFD 0.8 V)
t OFF
Dwg. WP-031-1
RS
Dwg. EP-006-15
Figure 1 -- Load-Current Paths
Figure 2 -- Current-Decay Waveforms
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A3955
Full-Bridge PWM Microstepping Motor Driver
reference value, resulting in increased motor performance in microstepping applications. For a given level of ripple current, slow decay affords the lowest PWM frequency, which reduces heating in the motor and driver IC due to a corresponding decrease in hysteretic core losses and switching losses respectively. Slow decay also has the advantage that the PWM load current regulation can follow a more rapidly increasing reference before the PWM frequency drops into the audible range. For these reasons slow-decay mode is typically used as long as good current regulation can be maintained. Under some circumstances slow-decay mode PWM can fail to maintain good current regulation: 1) The load current will fail to regulate in slow-decay mode due to a sufficiently negative back-EMF voltage in conjunction with the low voltage drop across the load during slow decay recirculation. The negative back-EMF voltage can cause the load current to actually increase during the slow decay off time. A negative back-EMF voltage condition commonly occurs when driving stepping motors because the phase lead of the rotor typically causes the back-EMF voltage to be negative towards the end of each step (see figure 3A). 2) When the desired load current is decreased rapidly, the slow rate of load current decay can prevent the current from following the desired reference value. 3) When the desired load current is set to a very low value, the current-control loop can fail to regulate due to its minimum duty cycle, which is a function of the user-selected value of tOFF and the minimum on-time pulse width ton(min) that occurs each time the PWM latch is reset.
B -- Fast-Decay A -- Slow-Decay
Fast Current-Decay Mode. When VPFD 0.8 V, the device
is in fast current-decay mode (both the sink and source drivers are disabled when the load current reaches ITRIP). During the fixed off-time, the load inductance causes the current to flow from ground to the load supply via the motor winding, groundclamp and flyback diodes (see figure 1). Because the full motor supply voltage is across the load during fast-decay recirculation, the rate of load current decay is rapid, producing a high ripple current for a given fixed off-time (see figure 2). This rapid rate of decay allows good current regulation to be maintained at the cost of decreased average current accuracy or increased driver and motor losses.
C -- Mixed-Decay
Figure 3 -- Sinusoidal Drive Currents
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A3955
Full-Bridge PWM Microstepping Motor Driver
With increasing values of tOFF, switching losses will decrease, low-level load-current regulation will improve, EMI will be reduced, the PWM frequency will decrease, and ripple current will increase. A value of tOFF can be chosen for optimization of these parameters. For applications where audible noise is a concern, typical values of tOFF are chosen to be in the range of 15 to 35 s.
Mixed Current-Decay Mode. If VPFD is between 1.1 V
and 3.1 V, the device will be in a mixed current-decay mode. Mixed-decay mode allows the user to achieve good current regulation with a minimum amount of ripple current and motor/driver losses by selecting the minimum percentage of fast decay required for their application (see also the Stepper Motor Applications section). As in fast current-decay mode, mixed-decay starts with the sink and source drivers disabled after the load current reaches ITRIP. When the voltage at the RC terminal decays to a value below VPFD, the sink drivers are re-enabled, placing the device in slow current-decay mode for the remainder of the fixed off-time (figure 2). The percentage of fast decay (PFD) is user determined by VPFD or two external resistors. PFD = 100 ln (0.6[R1+R2]/R2) where:
VCC R1 PFD R2
RC Blanking. In addition to determining the fixed off-time of
the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the currentsense comparator when the outputs are switched by the internal current-control circuitry (or by the PHASE input, or when the device is enabled with the DAC data inputs). The comparator output is blanked to prevent false over-current detections due to reverse recovery currents of the clamp diodes, and/or switching transients related to distributed capacitance in the load. During internal PWM operation, at the end of the tOFF time, the comparator's output is blanked and CT begins to be charged from approximately 0.22VCC by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on CT reaches approximately 0.6VCC. The blanking time, tBLANK, can be calculated as: tBLANK = RTCT ln (RT/[RT - 3 k]). When a transition of the PHASE input occurs, CT is discharged to near ground during the crossover delay time (the crossover delay time is present to prevent simultaneous conduction of the source and sink drivers). After the crossover delay, CT is charged by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on CT reaches approximately 0.6VCC. Similarly, when the device is disabled, via the DAC data inputs, CT is discharged to near ground. When the device is re-enabled, CT is charged by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on CT reaches approximately 0.6VCC. The blanking time, tBLANK, can be calculated as: tBLANK = RTCT ln ([RT - 1.1 k]/RT - 3 k). The minimum recommended value for CT is 470 pF 5 %. This value ensures that the blanking time is sufficient to avoid false trips of the comparator under normal operating conditions. For optimal regulation of the load current, this value for CT is recommended and the value of RT can be sized to determine tOFF.
D
EP 062
Fixed Off-Time. The internal PWM current-control circuitry
uses a one shot to control the time the driver(s) remain(s) off. The one-shot off-time, tOFF, is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminal to ground. The off-time, over a range of values of CT = 470 pF to 1500 pF and RT = 12 k to 100 k, is approximated by: tOFF RTCT. When the load current is increasing, but has not yet reached the sense-current comparator threshold (ITRIP), the voltage on the RC terminal is approximately 0.6VCC. When ITRIP is reached, the PWM latch is reset by the current-sense comparator and the voltage on the RC terminal will decay until it reaches approximately 0.22VCC. The PWM latch is then set, thereby re-enabling the driver(s) and allowing load current to increase again. The PWM cycle repeats, maintaining the peak load current at the desired value.
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A3955
Full-Bridge PWM Microstepping Motor Driver
Thermal Considerations. Thermal-protection circuitry
turns off all output transistors when the junction temperature reaches approximately +165C. This is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. The output transistors are re-enabled when the junction temperature cools to approximately +150C.
Stepper Motor Applications. The A3955 is used to optimize performance in microstepping/sinusoidal stepper-motor
drive applications (see figures 4 and 5). When the load current is increasing, the slow current-decay mode is used to limit the switching losses in the driver and iron losses in the motor. This also improves the maximum rate at which the load current can increase (as compared to fast decay) due to the slow rate of decay during tOFF. When the load current is decreasing, the mixed current-decay mode is used to regulate the load current to the desired level. This prevents tailing of the current profile caused by the back-EMF voltage of the stepper motor (see figure 3A).
BRIDGE A
V PFD V REF
VBB
BRIDGE B
D 1B D2B
PHASE B +5 V
1 2 3
16 15
47 F
9 10
8 7 6 5 4 3 2 1
+
D 0A
14 13 12 11 11 10 9 11
470 pF
30 k
4 LOGIC 5
0.5
12 LOGIC 13
0.5
+5 V PHASE A
6 7 8
D0B
47 F
14 15
V REF V PFD
Dwg. EP-047-3
D2A
D 1A
VBB
+
16
Figure 4 -- Typical Application
MIXED DECAY
SLOW DECAY
MIXED DECAY
SLOW DECAY
Dwg. WK-004-3
Figure 5 -- Microstepping/Sinusoidal Drive Current
470 pF
30 k
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A3955
Full-Bridge PWM Microstepping Motor Driver
Table 4 -- Step Sequencing
Bridge A Full Step 1 Half Step 1 Quarter Eighth Step Step 1 2 2 3 4 2 3 5 6 4 7 8 3 5 9 10 6 11 12 4 7 13 14 8 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PHASEA H H H H X L L L L L L L L L L L L L L L X H H H H H H H H H H H D2A H L L L L L L L H H H H H H H H H L L L L L L L H H H H H H H H D1A L H H L L L H H L L H H H H H L L H H L L L H H L L H H H H H L D0A L H L H L H L H L H L H H H L H L H L H L H L H L H L H H H L H ILOADA 70.7% 55.5% 38.2% 19.5% 0% -19.5% -38.2% -55.5% -70.7% -83.1% -92.4% -100% -100% -100% -92.4% -83.1% -70.7% -55.5% -38.2% -19.5% 0% 19.5% 38.2% 55.5% 70.7% 83.1% 92.4% 100% 100% 100% 92.4% 83.1% PHASEB H H H H H H H H H H H H X L L L L L L L L L L L L L L L X H H H D2B H H H H H H H H H L L L L L L L H H H H H H H H H L L L L L L L Bridge B D1B L L H H H H H L L H H L L L H H L L H H H H H L L H H L L L H H D0B L H L H H H L H L H L H L H L H L H L H H H L H L H L H L H L H ILOADB 70.7% 83.1% 92.4% 100% 100% 100% 92.4% 83.1% 70.7% 55.5% 38.2% 19.5% 0% -19.5% -38.2% -55.5% -70.7% -83.1% -92.4% -100% -100% -100% -92.4% -83.1% -70.7% -55.5% -38.2% -19.5% 0% 19.5% 38.2% 55.5%
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A3955
Full-Bridge PWM Microstepping Motor Driver
100 92.4
A
MAXIMUM FULL-STEP
TORQUE (141%)
0% 10
1/8 ST E
83.1
P
TEP
A ST N O C
1/4 S
ST
70.7
EP
T N TO
CURRENT IN PER CENT
3/8
R Q
EP
U
ST
E
55.5
1/
2
5/8
38.2
ST
EP
3/4
STE
P
19.5
7/8 ST
EP
B 19.5 A
FULL STEP B 38.2 55.5 70.7 CURRENT IN PER CENT 83.1 92.4 100
Dwg. GK-020-1
Figure 5 -- Current and Displacement Vectors
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A3955
Full-Bridge PWM Microstepping Motor Driver
B package 16-pin DIP
.750 [19.05] 16 .010 [0.25] .250 [6.35] A 1 2 .430 [10.92] .300 [7.62]
.210 [5.33] MAX .130 [3.30] .005 [1.27] .060 [1.52] .018 [0.46] .100 [2.54]
All dimensions nominal, not for tooling use (reference JEDEC MS-001 BB) Dimensions in inches, metric dimensions (mm) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area
LB package 16-pin SOICW
10.30 4 16 0.27 0.65 1.27
7.50 A
10.30
9.50 0.84 2.25
1
2 0.25
B
PCB Layout Reference View
16X 0.10 C 0.41 1.27 0.20
SEATING PLANE 2.65 MAX
C
SEATING PLANE GAUGE PLANE
All dimensions nominal, not for tooling use Dimensions in millimeters (reference JEDEC MS-013 AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Pins 4 and 13 fused internally A Terminal #1 mark area
B
Reference pad layout (reference IPC SOIC127P1030X265-16M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances
Copyright (c)1997-2007, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents, including U. S. Patent No. 5,684,427, or U.S. patents pending Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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